View CD40105BMS_196612.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CD40105BMS
December 1992
CMOS FIFO Register
Description
CD40105BMS is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flipflop, which stores a marker bit. A "1" signifies that the position's data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until that data have been transferred to the second location. The flag will remain low when all 16word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Continued on next page
Features
* 4 Bits x 16 Words * High Voltage Type (20V Rating) * Independent Asynchronous Inputs and Outputs * 3-State Outputs * Expandable in Either Direction * Status Indicators on Input and Output * Reset Capability * Standardized Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Bit Rate Smoothing * CPU/Terminal Buffering * Data Communications * Peripheral Buffering * Line Printer Input Buffers * Auto Dialers * CRT Buffer Memories * Radar Data Acquisition
Pinout
3 - STATE CONTROL 1 DIR SI D0 D1 D2 D3 VSS 2 3 4 5 6 7 8
CD40105BMS TOP VIEW
16 VDD 15 SO 14 DOR 13 Q0 12 Q1 11 Q2 10 Q3 9 MR
Functional Diagram
3-STATE CONTROL D0 D1 D2 D3 SHIFT IN SHIFT OUT 4 5 6 7 3 15 9 1 13 12 11 10 14 2 Q0 Q1 Q2 Q3 DATA-OUT READY DATA-IN READY
MASTER RESET
VDD = 16 VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3353
7-1317
CD40105BMS
Unloading Data - As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFTOUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. Cascading - The CD40105BMS can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions (see Figures 9 and 11). 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the control logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W
Logic Diagram
MASTER RESET 2 DATA IN READY (DIR) SHIFT OUT
*
15
1
*
3 - STATE CONTROL (OUTPUT ENABLE)
*
9
SHIFT IN
*
3 POSITIONS
DATA READY 14 (DOR) R 16 S Q Q R S Q
R S Q
R 1 S
Q Q
R 2 S
Q Q
4 - 15
* D0 * D1 * D2 *
D3
4 CL 5 6 7 POS 1 POS 2 VDD POS 3 POS 16 CL CL CL CL CL CL CL CL 4 LATCHES 4 LATCHES 4 LATCHES 4 LATCHES 3 STATE OUTPUT BUFFERS
13 Q0 12 Q1 11 Q2 10 Q3
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION NETWORK
DETAIL OF LATCHES p n CL CL p n VSS CL
7-1318
Specifications CD40105BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional (Note 4) VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 VDD = 18V 3 +25oC, +25oC, +25oC, LIMITS TEMPERATURE +25 C +125 C -55 C +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 V V V V A A A -55oC -55oC
o o o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 14.95 0.53 1.4 3.5 -2.8 0.7
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
VOH > VOL < VDD/2 VDD/2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC
7-1319
Specifications CD40105BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 LIMITS TEMPERATURE +25oC +125oC -55oC MIN MAX 0.4 12 0.4 UNITS A A A
PARAMETER Tri-State Output Leakage
SYMBOL IOZH
CONDITIONS (NOTE 1) VIN = VDD or GND VOUT = VDD VDD = 20V
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 4. VDD = 2.8V/3.0V, RL = 100K to VDD VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN 1.5 1.11 MAX 370 500 320 432 4 5.4 280 378 200 270 UNITS ns ns ns ns s s ns ns ns ns MHz MHz
PARAMETER Propagation Delay Shift Out or Reset to Data-Out Ready Propagation Delay Shift In to Data-In Ready Propagation Delay Ripple through Delay Input to Output Propagation Delay 3-State Control to Data Out Transition Time
SYMBOL TPHL1
CONDITIONS (NOTE 1) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V (Note 1, 2), VIN = VDD or GND
TPHL2
+25oC +125oC, -55oC
TPLH3
+25oC +125oC, -55oC +25oC +125oC, -55oC
TPZH
TTHL TTLH FCL
+25oC +125oC, -55oC
Maximum Shift-In or Shift-Out Rate NOTES:
+25oC +125oC, -55oC
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage VOL VOL VOH VOH VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load 1, 2 1, 2 1, 2 1, 2 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 4.95 9.95 50 mV V V MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV
7-1320
Specifications CD40105BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) SYMBOL IOL5 CONDITIONS VDD = 5V, VOUT = 0.4V NOTES 1, 2 TEMPERATURE +125oC -55 C Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55oC Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC -55o Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 C +125oC -55 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2
oC o
MIN 0.36 0.64 0.9 1.6 2.4 4.2 7 3 4 -
MAX -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 180 130 2 1.4 130 90 420 380 250 120 80 100 80 15 15 15 15 15 15 15 5 5
UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns s s ns ns ns ns ns ns ns ns ns MHz MHz s s s s s s s s s
+125oC -55 C
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125o
C
-55oC Input Voltage Low Input Voltage High Propagation Delay Shift or Reset to Data Out Ready Propagation Delay Ripple through Delay Input to Output Propagation Delay Shift-In to Data-In Ready Propagation Delay Shift Out to QN Out VIL VIH TPHL1 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V TPLH3 VDD = 10V VDD = 15V TPHL2 VDD = 10V VDD = 15V TPHL4 TPLH4 VDD = 5V VDD = 10V VDD = 15V Propagation Delay 3-State Control to Data Out Propagation Delay 3-State Control to Data Out Maximum Shift-In or Shift-Out Rate Maximum Shift-In or Shift-Out Rise Time TPZH TPZL TTHZ TPLZ FCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V TR VDD = 5V VDD = 10V VDD = 15V Maximum Shift-In Fall Time TF VDD = 5V VDD = 10V VDD = 15V Maximum Shift-Out Fall Time TF VDD = 5V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2 1, 2 3 3 3 3 3 3 3 3 3 +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25 C +25oC +25
oC o
+25oC +25oC +25
oC
+25oC +25oC +25
oC
+25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
7-1321
Specifications CD40105BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Master Reset Pulse Width SYMBOL TWH CONDITIONS VDD = 5V VDD = 10V VDD = 15V Data-In Ready Pulse Width TWL VDD = 5V VDD = 10V VDD = 15V Data-Out Ready Pulse Width TWL VDD = 5V VDD = 10V VDD = 15V Minimum Shift Out Pulse Width TWL VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time TSU VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Shift In Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC +25
oC o
MIN -
MAX 200 90 60 520 200 140 440 180 130 180 75 55 0 0 0 350 150 120 200 80 60 7.5
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
+25oC +25oC +25
oC
+25o
C
+25oC +25
oC
+25oC +25 C +25o C +25oC +25oC +25
oC o
+25oC +25 C +25
oC o
+25oC +25
oC
+25oC
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
7-1322
Specifications CD40105BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic Burn-In Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 2, 10 - 14 2, 10 - 14 2, 10 - 14 GROUND 1, 3 - 9, 15 8 1, 8, 9 8 VDD 16 1, 3 - 7, 9, 15, 16 16 1, 3 - 7, 9, 15, 16 2, 10 - 14 3, 15 4-7 9V -0.5V 50kHz 25kHz
7-1323
CD40105BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
4 68
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
POWER DISSIPATION PER GATE (PD) (W) (ALL Q OUTPUTS LOADED) 106
8 6 4 2
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
105
8 6 4
200 SUPPLY VOLTAGE (VDD) = 5V
150
104
2 8 6 4
10V 10V 5V
100 10V 50 15V
103
2 8 6 4
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68 2
102 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF)
2
1
103 10 102 INPUT FREQUENCY (fIN) (kHz)
104
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY
7-1324
CD40105BMS
INPUT BUFFERS D0 D1 D2 D3 4 5 6 7 4 x 16 DATA REGISTER
OUTPUT BUFFERS 13 Q0 12 Q1 11 Q2 10 Q3 1 SI DOR D0 Q0 D1 Q1 D2 Q2 D3 Q3 DIR MR SO SI DOR D0 Q0 D1 Q1 D2 Q2 D3 Q3 DIR MR SO
DATA-IN READY (DIR) 2 CONTROL LOGIC
3-STATE CONTROL 14 DATA-OUT READY (DOR)
3 SHIFT IN (SI) 9 MASTER RESET (MR)
15 SHIFT OUT (SO)
FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM
FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG
MASTER RESET SHIFT IN (DATA VALID) INPUTS 2s* SHIFT-IN PULSES HAVE NO EFFECT
SHIFT OUT SHIFT-OUT PULSES HAVE NO EFFECT INPUT READY (CLEAR OUT) OUTPUTS OUTPUT READY (CLEAR OUT) 2s**
DATA IN (Dn) INPUTS 3-STATE (OUTPUT ENABLE) DATA OUT*** 10 11 10 011 0 10 10 1 0 HIGH Z 1 0 1 1 1 0 INVALID
(UNKNOWN)
*AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16 **AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1 ***DATA VALID goes to high level in advance of the DATA OUT
by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V, and 20ns at VDD = 15V for CL = 50pF and TA = 25oC
FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS
7-1325
CD40105BMS
SHIFT IN SI DOR D0 Q0 D1 D2 D3 Q1 Q2 Q3 SI DOR D0 Q0 D1 D2 D3 Q1 Q2
DATA OUT READY
MR DIR SO 8 BIT DATA SI DOR D0 Q0 D1 D2 D3 Q1 Q2 Q3
Q3 MR DIR SO 8 BIT DATA SI DOR D0 Q0 D1 D2 D3 Q1 Q2
MR DIR SO
Q3 MR DIR SO
DATA IN READY
SHIFT OUT
*MASTER
RESET
*Pulse must be applied for cascading by 16 N bits.
FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION: BOND PADS:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1326

▲Up To Search▲

Price & Availability of CD40105BMS

	To Download CD40105BMS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .